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? semiconductor components industries, llc, 2015 june, 2015 ? rev. 14 1 publication order number: ncp1251/d ncp1251 current-mode pwm controller for off-line power supplies the ncp1251 is a highly integrated pwm controller capable of delivering a rugged and high performance offline power supply in a tiny tsop?6 package. with a supply range up to 28 v, the controller hosts a jittered 65 khz or 100 khz switching circuitry operated in peak current mode control. when the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 khz. as the power further goes down, the part enters skip cycle while limiting the peak current. over power protection (opp) is a difficult exercise especially when no?load standby requirements drive the converter specifications. the on proprietary integrated opp lets you harness the maximum delivered power without affecting your standby performance simply via two external resistors. a latched over voltage protection (ovp) is combined on the same pin. for ease of implementation, a latched ovp also monitors the v cc line. they offer an efficient protection in case of optocoupler destruction or adverse open loop operation. finally, a timer?based short?circuit protection offers the best protection scheme, letting you precisely select the protection trip point irrespective of a loose coupling between the auxiliary and the power windings. features ? fixed?frequency 65 or 100 khz current?mode control operation ? internal and adjustable over power protection (opp) circuit ? frequency foldback down to 26 khz and skip?cycle in light load conditions ? internal ramp compensation ? internal fixed 4 ms soft?start ? 100 ms timer?based auto?recovery short?circuit protection ? frequency jittering in normal and frequency foldback modes ? option for auto?recovery or latched short?circuit protection ? ovp input for improved robustness ? up to 28 v v cc operation ? latched or auto?recovery ovp protection on v cc ? +300 ma / ?500 ma source/sink drive capability ? less than 100 mw standby power at high line ? eps 2.0 compliant ? these are pb?free devices typical applications ? ac?dc converters for tvs, set?top boxes and printers ? offline adapters for notebooks and netbooks pin connections 1 3 cs gnd 2 opp/latch 4 drv 6 (top view) 5 v cc tsop?6 (sot23?6) sn suffix case 318g style 13 marking diagram fb www. onsemi.com (note: microdot may be in either location) 1 5xyayw 1 5xy = specific device code x = a or u y = a, 2, c, d, or f a = assembly location y = year w = work week = pb?free package see detailed ordering, marking and shipping information on page 2 of this data sheet. ordering information
ncp1251 www. onsemi.com 2 1 2 3 6 4 5 ncp1251 vbulk . . ramp comp. opp vo u t ovp . figure 1. typical application example pin n pin name function pin description 1 gnd ? the controller ground. 2 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 3 opp/ovp adjust the over power protection latches off the part a resistive divider from the auxiliary winding to this pin sets the opp compensation level. when brought above 3 v, the part is fully latched off. 4 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a means to introduce ramp compensation. 5 v cc supplies the controller this pin is connected to an external auxiliary voltage and supplies the controller. when the v cc exceeds a certain level, the part permanently latches off. 6 drv driver output the driver?s output to an external mosfet gate. options controller frequency ocp v cc ovp ovp/otp ncp1251asn65t1g 65 khz latched latched latched ncp1251bsn65t1g 65 khz autorecovery latched latched ncp1251csn65t1g 65 khz autorecovery autorecovery latched ncp1251fsn65t1g 65 khz autorecovery latched latched ncp1251asn100t1g 100 khz latched latched latched NCP1251BSN100T1G 100 khz autorecovery latched latched note: f version has a different foldback scheme for improved efficiency. ordering information device package marking ocp protection v cc ovp protection switching frequency package shipping ? ncp1251asn65t1g 5aa latch latch 65 khz tsop?6 (pb?free) 3000 / tape & reel ncp1251bsn65t1g 5a2 autorecovery latch 65 khz ncp1251csn65t1g 5ae autorecovery autorecovery 65 khz ncp1251fsn65t1g 5af autorecovery latch 65 khz ncp1251asn100t1g 5ac latch latch 100 khz NCP1251BSN100T1G 5ad autorecovery latch 100 khz ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1251 www. onsemi.com 3 figure 2. internal circuit architecture s r q q 65 khz 100 khz clock vdd frequency modulation vcc drv vcc logic management and fault timer vdd power on reset rramp leb vdd rfb / 4.2 ipflag 4 ms ss power on reset ipflag gnd cs fb 600?ns time constant opp frequency foldback vskip vlatch the soft?start is activated during: ? the startup sequence ? the auto?recovery burst mode + vlimit vopp vlimit + vopp vfold s r q q clamp 20us time constant vovp 1?us blanking up counter 4 rst ovp gone? vfb < 1.05 v ? setpoint = 250 mv 250 mv peak current freeze uvlo bo rlimit iscr
ncp1251 www. onsemi.com 4 maximum ratings table symbol rating value unit v cc power supply voltage, v cc pin, continuous voltage 28 v v drvtran maximum drv pin voltage when drv in h state, transient voltage (note 1) v cc + 0.3 v maximum voltage on low power pins cs, fb and opp ?0.3 to 10 v iopp maximum injected negative current into the opp pin (pin 3) ?2 ma i scr maximum continuous current into the v cc pin while in latch mode 3 ma r ja thermal resistance junction?to?air 360 c/w t j,max maximum junction temperature 150 c storage temperature range ?60 to +150 c esd capability, human body model (hbm), all pins 2 kv esd capability, machine model (mm) 200 v esd capability, charged device model (cdm) 1 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the transient voltage is a voltage spike injected to drv pin being in high state. maximum transient duration is 100 ns. 2. this device series contains esd protection and exceeds the following tests: human body model 2000 v per jesd22, method a114e. machine model method 200 v per jesd22, method a115a. charged device model per jedec standard jesd22?c101d 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78.
ncp1251 www. onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section vcc on v cc increasing level at which driving pulses are authorized 5 16 18 20 v vcc (min) v cc decreasing level at which driving pulses are stopped 5 8.2 8.8 9.4 v vcc hyst hysteresis vcc on ? vcc (min) 5 6.0 v v zener clamped v cc when latched off / burst mode activation @ i cc = 500 a 5 7.0 v icc1 start?up current 5 15 a icc2 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 0 nf 5 1.4 2.2 ma icc3 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 1 nf 5 2.1 3.0 ma icc2 internal ic consumption with i fb = 50 a, f sw = 100 khz and c l = 0 nf 5 1.7 2.5 ma icc3 internal ic consumption with i fb = 50 a, f sw = 100 khz and c l = 1 nf 5 3.1 4.0 ma iccstby internal ic consumption while in skip cycle (v cc = 12 v, driving a typical 6 a/600 v mosfet) 5 550 a icc latch current flowing into v cc pin that keeps the controller latched (note 4) t j = ?40 c to +125 c t j = 0 c to +125 c 5 40 32 a r lim current?limit resistor in series with the latch scr 5 4.0 k drive output t r output voltage rise?time @ c l = 1 nf, 10?90% of output signal 6 40 ns t f output voltage fall?time @ c l = 1 nf, 10?90% of output signal 6 30 ns r oh source resistance 6 13 r ol sink resistance 6 6.0 i source peak source current, v gs = 0 v ? (note 5) 6 300 ma i sink peak sink current, v gs = 12 v ? (note 5) 6 500 ma v drvlow drv pin level at v cc close to vcc (min) with a 33 k resistor to gnd 6 8.0 v v drvhigh drv pin level at v cc = 28 v ? drv unloaded 6 10 12 14 v current comparator i ib input bias current @ 0.8 v input level on pin 4 4 0.02 a v limit1 maximum internal current setpoint ? t j = 25 c ? pin 3 grounded 4 0.744 0.8 0.856 v v limit2 maximum internal current setpoint ? t j = ?40 c to 125 c ? pin 3 grounded 4 0.72 0.8 0.88 v v fold default internal voltage set point for frequency foldback trip point ? 45% of v limit 3 357 mv v freeze internal peak current setpoint freeze ( 31% of v limit ) 3 250 mv t del propagation delay from current detection to gate off?state 4 100 150 ns t leb leading edge blanking duration 4 300 ns tss internal soft?start duration activated upon startup, auto?recovery ? 4 ms ioppo setpoint decrease for pin 3 biased to ?250 mv ? (note 6) 3 31.3 % ioopv voltage setpoint for pin 3 biased to ?250 mv ? (note 6), t j = 25 c 3 0.51 0.55 0.60 v ioopv voltage setpoint for pin 3 biased to ?250 mv ? (note 6), t j = ?40 c to 125 c 3 0.50 0.55 0.62 v iopps setpoint decrease for pin 3 grounded 3 0 % product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. for design robustness, we recommend to inject 60 a as a minimum at the lowest input line voltage. 5. guaranteed by design 6. see characterization table for linearity over negative bias voltage 7. a 1 m resistor is connected from pin 3 to the ground for the measurement.
ncp1251 www. onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating internal oscillator f osc oscillation frequency (65 khz version) ? 61 65 71 khz f osc oscillation frequency (100 khz version) ? 92 100 108 khz d max maximum duty?cycle ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? 5 % f swing swing frequency ? 240 hz feedback section r up internal pull?up resistor 2 20 k r eq equivalent ac resistor from fb to gnd 2 16 k i ratio pin 2 to current setpoint division ratio ? 4.2 v freeze feedback voltage below which the peak current is frozen 2 1.05 v frequency foldback v fold frequency foldback level on the feedback pin ? 45% of maximum peak current ? 1.5 v v foldf frequency foldback level on the feedback pin ? 59% of maximum peak current (f version only) ? 1.9 v f trans transition frequency below which skip?cycle occurs ? 22 26 30 khz v fold,end end of frequency foldback feedback level, f sw = f min 350 mv v foldf,end end of frequency foldback feedback level, f sw = f min (f version only) 1.5 v v skip skip?cycle level voltage on the feedback pin ? 300 mv skip hysteresis hysteresis on the skip comparator ? (note 5) ? 30 mv internal slope compensation v ramp internal ramp level @ 25 c ? (note 7) 4 2.5 v r ramp internal ramp resistance to cs pin 4 20 k protections v latch latching level input 3 2.7 3 3.3 v t latch?blank blanking time after drive turn off 1 1.0 s t latch?count number of clock cycles before latch confirmation ? 4.0 t latch?del ovp detection time constant 1 600 ns timer internal auto?recovery fault timer duration ? 100 130 160 ms v ovp latched over voltage protection on the v cc rail 5 24 25.5 27 v t ovpdel delay before ovp on v cc confirmation 5 20 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. for design robustness, we recommend to inject 60 a as a minimum at the lowest input line voltage. 5. guaranteed by design 6. see characterization table for linearity over negative bias voltage 7. a 1 m resistor is connected from pin 3 to the ground for the measurement.
ncp1251 www. onsemi.com 7 typical characteristics 75 76 77 78 79 80 81 82 83 84 85 ?50 ?25 0 25 50 75 100 125 d max (%) temperature ( c) figure 3. 60 62 64 66 68 70 72 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 4. f sw (khz) 21 22 23 24 25 26 27 28 29 30 31 temperature ( c) figure 5. ?50 ?25 0 25 50 75 100 125 f trans (khz) 140 190 240 290 340 390 440 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 6. f _swing (hz) 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 0.87 0.89 temperature ( c) figure 7. v limit (mv) ?50 ?25 0 25 50 75 100 125 190 240 290 340 390 440 490 140 v lskip (mv) ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 8. f sw = 65 khz
ncp1251 www. onsemi.com 8 typical characteristics 19 24 29 34 39 44 ioop o (%) ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 9. 0.5 0.52 0.54 0.56 0.58 0.6 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 10. ioop v (v) 15.9 16.4 16.9 17.4 17.9 18.4 18.9 19.4 19.9 v cc(on) (v) temperature ( c) figure 11. ?50 ?25 0 25 50 75 100 125 8.1 8.3 8.5 8.7 8.9 9.1 9.3 9.5 v cc(min) (v) temperature ( c) figure 12. ?50 ?25 0 25 50 75 100 125 5 6 7 8 9 10 11 12 13 14 temperature ( c) figure 13. ?50 ?25 0 25 50 75 100 125 v cc(hyst) (v) 0 2 4 6 8 10 12 14 16 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 14. i cc1 ( a)
ncp1251 www. onsemi.com 9 typical characteristics 0 0.5 1 1.5 2 temperature ( c) figure 15. i cc2 (ma) ?50 ?25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 16. 0 2 4 6 8 10 i cc3 (ma) v zener (v) temperature ( c) figure 17. ?50 ?25 0 25 50 75 100 125 0 5 10 15 20 25 30 temperature ( c) figure 18. ?50 ?25 0 25 50 75 100 125 i cclatch ( a) 90 140 190 240 290 340 390 t leb (v) temperature ( c) figure 19. ?50 ?25 0 25 50 75 100 125 0 20 40 60 80 100 120 140 160 temperature ( c) figure 20. ?50 ?25 0 25 50 75 100 125 req (k ) f sw = 65 khz f sw = 65 khz
ncp1251 www. onsemi.com 10 typical characteristics 3.6 3.8 4 4.2 4.4 4.6 4.8 iratio (?) temperature ( c) figure 21. ?50 ?25 0 25 50 75 100 125 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 22. v latch (v) 0 20 40 60 80 100 t rise (ns) temperature ( c) figure 23. ?50 ?25 0 25 50 75 100 125 0 20 40 60 80 100 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 24. t fall (ns) 2 3 4 5 6 7 8 9 10 11 r ol ( ) temperature ( c) figure 25. ?50 ?25 0 25 50 75 100 125 5 10 15 20 25 30 35 r oh ( ) temperature ( c) figure 26. ?50 ?25 0 25 50 75 100 125
ncp1251 www. onsemi.com 11 typical characteristics 0 20 40 60 80 100 v ovp_del ( s) temperature ( c) figure 27. ?50 ?25 0 25 50 75 100 125 7 8 9 10 11 12 13 14 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 28. v drv_low (v) 8.9 9.4 9.9 10.4 10.9 11.4 11.9 12.4 12.9 v drv_high (v) temperature ( c) figure 29. ?50 ?25 0 25 50 75 100 125 2.9 3.4 3.9 4.4 4.9 t ss (ms) temperature ( c) figure 30. ?50 ?25 0 25 50 75 100 125 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 v fold(fb) (v) temperature ( c) figure 31. ?50 ?25 0 25 50 75 100 125 350 352 354 356 358 360 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 32. v fold(cs) (mv)
ncp1251 www. onsemi.com 12 typical characteristics 0.29 0.31 0.33 0.35 0.37 0.39 0.41 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 33. v fold_end (v) 190 240 290 340 390 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 34. v skip (mv) 190 240 290 340 390 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 35. v freeze (mv) 0.7 0.9 1.1 1.3 1.5 1.7 v freeze(fb) (v) temperature ( c) figure 36. ?50 ?25 0 25 50 75 100 125 90 100 110 120 130 140 150 160 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 37. timer (ms) 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3 .5 i cc (ma) adapter output current (a) figure 38. controller consumption vs. adapter output current f sw = 65 khz
ncp1251 www. onsemi.com 13 typical characteristics v ovp (v) 26.9 ?50 ?25 0 25 50 75 100 125 temperature ( c) figure 39. 26.4 25.9 25.4 24.9 24.4 23.9
ncp1251 www. onsemi.com 14 application information introduction the ncp1251 implements a standard current mode architecture where the switch?off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part?count and cost effectiveness are the key parameters, particularly in low?cost ac?dc adapters, open?frame power supplies etc. capitalizing on the ncp120x series success, the ncp1251 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non?dissipative opp. ? current?mode operation with internal ramp compensation : implementing peak current mode control at a fixed 65 khz or 100 khz, the ncp1251 offers an internal ramp compensation signal that can easily by summed with the sensed current. sub harmonic oscillations are eliminated via the inclusion of a single resistor in series with the current?sense information. ? internal opp : by routing a portion of the negative voltage present during the on?time on the auxiliary winding to the dedicated opp pin (pin 3), the user has a simple and non?dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage down to ?250 mv, then a peak current reduction down to 31.3% typical can be achieved. for an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 v. ? low startup current : achieving a low no?load standby power always represents a difficult exercise when the controller draws a significant amount of current during start?up. due to its proprietary architecture, the ncp1251 is guaranteed to draw less than 15 a typical, easing the design of low standby power adapters. ? emi jittering : an internal low?frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps by spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering remains active in frequency foldback mode. ? frequency foldback capability : a continuous flow of pulses is not compatible with no?load/light?load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 v, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. when the feedback pin reaches 1.05 v, the peak current setpoint is internally frozen and the frequency continues to decrease. it can go down to 26 khz (typical) reached for a feedback level of roughly 350 mv. at this point, if the power continues to drop, the controller enters classical skip?cycle mode. ? internal soft?start : a soft?start precludes the main power switch from being stressed upon start?up. in this controller, the soft?start is internally fixed to 4 ms. the soft?start is activated when a new startup sequence occurs or during an auto?recovery hiccup. ? ovp input : the ncp1251 includes a latch input (pin 3) that can be used to sense an overvoltage condition on the adapter. if this pin is brought higher than the internal reference voltage v latch , then the circuit permanently latches off. the v cc pin is pulled down to a fixed level, keeping the controller latched. the latch reset occurs when the user disconnects the adapter from the mains and lets the v cc falls below the v cc reset. ? latched ovp on v cc : it is sometimes interesting to implement a circuit protection by sensing the v cc level. this is what the ncp1251 does by monitoring its v cc pin. when the voltage on this pin exceeds 25 v typical, the pulses are immediately stopped and the part latches off. the vcc is maintained to 7 v typical and remains in this state until the user unplugs the power supply. ? short?cir cuit protection : short?circuit and especially over?load protections are difficult to implement for transformers with high leakage inductance between auxiliary and power windings (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8 v maximum peak current limit is activated (or less when opp is used), an error flag is asserted and a time period starts, thanks to an internal timer. if the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch?off phase, operating in a low?frequency burst?mode. when the fault is cleared, the smps resumes operation. please note that some versions offer an auto?recovery mode as described and some latch off in case of a short circuit. start?up sequence the ncp1251 start?up voltage is made purposely high to permit a large energy storage in a small v cc capacitor value. this helps to operate with a small start?up current which, together with a small v cc capacitor, will not hamper the start?up time. to further reduce the standby power, the start?up current of the controller is extremely low, below 15 a maximum. the start?up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation.
ncp1251 www. onsemi.com 15 11 1 r1 200k 10 r2 200k 3 r3 200k 5 d1 1n4007 12 d2 1n4007 cbulk 22uf c1 4.7uf d3 1n4007 d4 1n4007 input mains 4 2 d5 1n4935 c3 47uf d6 1n4148 vcc aux. figure 40. the startup resistor can be connected to the input mains for further power dissipation reduction the first step starts with the calculation of the v cc capacitor which will supply the controller when it operates until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 ms and 20 ms. if we consider we need at least an ener gy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: cv cc i cc t 1 vcc on vcc min 3m 10m 9 3.3 f (eq. 1) let us select a 4.7 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t 1 . the v cc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 to the vcc on of the ic, 18 v typical. this current has to be selected to ensure a start?up at the lowest mains (85 v rms) to be less than 3 s (2.5 s for design mar gin): i charge vcc on c vcc 2.5 18 4.7 2.5 34 a (eq. 2) if we account for the 15 a that will flow inside the controller, then the total charging current delivered by the start?up resistor must be 49 a. if we connect the start?up network to the mains (half?wave connection then), we know that the average current flowing into this start?up resistor will be the smallest when v cc reaches the vcc on of the controller: i cvcc,min v ac,rms 2 vcc on r start up (eq. 3) to make sure this current is always greater than 49 a, then the minimum value for r start?up can be extracted: r start up v ac,rms 2 vcc on i cvcc,min 85 1.414 18 49 413.5 k (eq. 4 ) this calculation is purely theoretical, and assumes a constant charging current. in reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the v cc capacitor. hence, a decrease in charging current and an increase of the start?up resistor, thus reducing the standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter. if we chose the 413 k resistor as suggested by equation 4, the dissipated power at high line amounts to: p rstart up v ac,peak 2 4r start up 230 2
2 4 413k (eq. 5) 230 2 0.827meg 64 mw now that the first v cc capacitor has been selected, we must ensure that the self?supply does not disappear when in no?load conditions. in this mode, the skip?cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the v cc capacitor. if this ripple is too large, chances exist to touch the vcc min and reset the controller into a new start?up sequence. a solution is to grow this capacitor but it will obviously be de trimental to the start?up time. the option offered in figure 40 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. however, this component is separated from the v cc pin via a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self?supply of the controller without jeopardizing the start?up time and standby power. a capacitor ranging from 22 to 47 f is the typical value for this device. one note on the start-up current. if reducing it helps to improve the standby power, its value cannot fall below a certain level at the minimum input voltage. failure to inject
ncp1251 www. onsemi.com 16 enough current (30 a) at low line will turn a converter in fault into an auto-recovery mode since the scr won?t remain latched. to build a sufficient design margin, we recommend to keep at least 60 a flowing at the lowest input line (80 v rms for 85 v minimum for instance). an excellent solution is to actually combine x2 discharge and start-up networks as proposed in figure 13 of application note and8488/d. internal over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip?cycle disturbance brought by the current?sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. during the power switch on?time, this point dips to ?nv in , n being the turns ratio between the primary winding and the auxiliary winding. the negative plateau observed on figure 42 will have an amplitude dependant on the input voltage. the idea implemented in this chip is to sum a portion of this negative swing with the 0.8 v internal reference level. for instance, if the voltage swings down to ?150 mv during the on time, then the internal peak current set point will be fixed to 0.8 ? 0.150 = 650 mv. the adopted principle appears in figure 42 and shows how the final peak current set point is constructed. 1 v(24) 464u 472u 480u 488u 496u time (s) ?40.0 ?20.0 0 20.0 40.0 v(24) (v) 1 on?time 1 v(24) ?40.0 ?20.0 0 20.0 40.0 1 off?time figure 41. the signal obtained on the auxiliary winding swings negative during the on?time n 1 (v out +v f ) ?n 2 v bulk let?s assume we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to a 20% reduction or a set point voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 640m 800m ?160 mv (eq. 6)
ncp1251 www. onsemi.com 17 vdd re f opp + ? from fb reset cs vcc aux roppu swings to: vout during toff ?n v in during ton iopp r oppl sum2 k1 k2 0.8 v 5% ref = 0.8 v + vopp (v o p p is negativ e) this p oin t will be adjusted to reduce the ref at hi line to the desired level. figure 42. the opp circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference let us assume that we have the following converter characteristics: v out = 19 v v in = 85 to 265 v rms n 1 = n p :n s = 1:0.25 n 2 = n p :n aux = 1:0.18 given the turns ratio between the primary and the auxiliary windings, the on?time voltage at high line (265 vac) on the auxiliary winding swings down to: v aux ?n 2 v in,max ?0.18 375 ?67.5 v (eq. 7) to obtain a level as imposed by equation 6, we need to install a divider featuring the following ratio: div 0.16 67.5 2.4m (eq. 8) if we arbitrarily fix the pull?down resistor r oppl to 1 k , then the upper resistor can be obtained by: r oppu 67.5 0.16 0.16 1k 421 k (eq. 9) if we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve (figure 43): 80% peak current setpoint v bulk 375 100% figure 43. the peak current regularly reduces down to 20% at 375 vdc the opp pin is surrounded by zener diodes stacked to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. to avoid this problem, the pin is internally clamped slightly below ?300 mv which means that if more current is injected before reaching the esd forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. given the value of r oppu , there is no risk in the present example.
ncp1251 www. onsemi.com 18 finally, please note that another comparator internally fixes the maximum peak current set point to 0.8 v even if the opp pin is inadvertently biased above 0 v. frequency foldback the reduction of no?load standby power associated with the need for improving the efficiency, requires a change to the traditional fixed?frequency type of operation. this controller implements a switching frequency foldback when the feedback voltage passes below a certain level, v fold , set around 1.5 v. at this point, the oscillator enters frequency foldback and reduces its switching frequency. the peak current setpoint follows the feedback pin until its level reaches 1.05 v. below this value, the peak current freezes to v fold /4.2 (250 mv or 31% of the maximum 0.8 v setpoint) and the only way to further reduce the transmitted power is to reduce the operating frequency down to 26 khz. this value is reached at a voltage feedback level of 350 mv typically. below this point, if the output power continues to decrease, the part enters skip cycle for the best noise?free performance in no?load conditions. figure 44 depicts the adopted scheme for the part. the ncp1251f version offers a means to improve light?load ef ficiency by folding the switching frequency sooner compared to the other versions. with the 1251 a, b and c versions, the minimum frequency is reached for v fb equals 350 mv. with the 1251f, this minimum frequency will be obtained at a feedback voltage equal to 1.5 v, naturally offering a better efficiency for lighter load conditions. figure 45 portrays the specific foldback scheme implemented in the ncp1251f. f sw v fb v cs v fb 65 khz 26 khz 350 mv v fold 3.4 v v fold 3.4 v 0.8 v 0.36 v fb v freeze 0.25 v 1.05 v 1.5 v 1.5 v max min max min v fold,end frequency peak current setpoint v fb min figure 44. by observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load figure 45. with ncp1251f, the frequency foldback occurs sooner as the load gets lighter.
ncp1251 www. onsemi.com 19 auto?recovery short?circuit protection in case of output short?circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than 100 ms, the driving pulses are stopped and the v cc pin slowly goes down to around 7 v. at this point, the controller wakes?up and the v cc builds up again due to the resistive starting network. when v cc reaches vcc on , the controller attempts to re?start, checking for the absence of the fault. if the fault is still there, the supply enters another cycle of so?called hiccup mode. if the fault has cleared, the power supply resumes normal operation. please note that the soft?start is activated during each of the re?start sequence. 1 vcc 2 vdrv 3 ilprim 500u 1.50m 2.50m 3.50m 4.50m time in seconds 445m 1.41 2.38 3.35 4.32 ilprim in amperes ?8.13 ?2.12 3.89 9.90 15.9 vcc in volts ?11.5 ?2.72 6.05 14.8 23.6 vdrv in volts plot1 2 1 3 cc v (t) drv v p l i ss 1 vcc 2 vdrv 3 ilprim 500u 1.50m 2.50m 3.50m 4.50m time in seconds 445m 1.41 2.38 3.35 4.32 ilprim in amperes ?8.13 ?2.12 3.89 9.90 15.9 vcc in volts ?11.5 ?2.72 6.05 14.8 23.6 vdrv in volts plot1 2 1 3 cc v drv v p l i ss figure 46. an auto?recovery hiccup mode is activated for faults longer than 100 ms (t) (t) slope compensation the ncp1251 includes an internal ramp compensation signal. this is the buffered oscillator clock delivered only during the on time. its amplitude is around 2.5 v at the maximum duty?cycle. ramp compensation is a known means used to cure sub harmonic oscillations in continuous conduction mode (ccm) operated current?mode converters. these oscillations take place at half the switching frequency and occur only during ccm with a duty?cycle greater than 50%. to lower the current loop gain, one usually injects between 50% and 100% of the inductor downslope. figure 47 depicts how internally the ramp is generated. please note that the ramp signal will be disconnected from the cs pin, during the off time. rsense rcomp 20k 0v 2.5 v cs + ? leb from fb setpoint latch reset on figure 47. inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in ccm operation.
ncp1251 www. onsemi.com 20 in the ncp1251 controller, the oscillator ramp features a 2.5 v swing reached at a 80% duty?ratio. if the clock operates at a 65 khz fre quency, then the available oscillator slope corresponds to: s ramp v ramp,peak d max t sw 2.5 0.8 15 (eq. 10) 208 kv sor208mv s in our flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s ratio of 1:0.25. the off?time primary current slope s p is thus given by: s p v out v f
n p n s l p ( 19 0.8 ) 4 770 103 ka s (eq. 11) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 103k 0.33 (eq. 12) 34 kv sor34mv s if we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 208 mv/ s, the divider ratio ( divratio ) between r comp and the internal 20 k resistor is: divratio 17m 208m 0.082 (eq. 13) the series compensation resistor value is thus: (eq. 14 ) r comp r ramp divratio 20k 0.082 1.6 k a resistor of the above value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small capacitor of 100 pf, from the current sense pin to the controller ground for an improved immunity to the noise. please make sure both components are located very close to the controller. latching off the controller the opp pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch?off the part. when the part is latched?off, the v cc pin is internally pulled down to around 7 v and the part stays in this state until the user cycles the v cc down and up again, e.g. by un?plugging the converter from the mains outlet. it is important to note that the scr maintains its latched state as long as the injected current stays above the minimum value of 30 a. as the scr delatches for an injected current below this value, it is the designer duty to make sure the injected current is high enough at the lowest input voltage. failure to maintain a sufficiently high current would make the device auto recover. a good design practice is to ensure at least 60 a at the lowest input voltage. the latch detection is made by observing the opp pin by a comparator featuring a 3 v reference voltage. however, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a 1 s blanking delay is introduced before the output of the ovp comparator is checked. then, the ovp comparator output is validated only if its high?state duration lasts a minimum of 600 ns. below this value, the event is ignored. then, a counter ensures that 4 successive ovp events have occurred before actually latching the part. there are several possible implementations, depending on the needed precision and the parameters you want to control. the first and easiest solution is the additional resistive divider on top of the opp one. this solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the opp divider during the on time. d2 1n4148 4 5 1 op p vlatch 10 8 9 vcc aux. winding opp roppl 1k roppu 421k 11 r3 5k c1 100p ovp figure 48. a simple resistive divider brings the opp pin above 3 v in case of a v cc voltage runaway above 18 v
ncp1251 www. onsemi.com 21 first, calculate the opp network with the above equations. then, suppose we want to latch off our controller when v out exceeds 25 v. on the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary winding. in case of voltage runaway for our 19 v adapter, the plateau will go up to: v aux,ovp 25 0.18 0.25 18 v (eq. 15) since our ovp comparator trips at a 3 v level, across the 1 k selected opp pulldown resistor, it implies a 3 ma current. from 3 v to go up to 18 v, we need an additional 15 v. under 3 ma and neglecting the series diode forward drop, it requires a series resistor of: r ovp v latch v vop v ovp r oppl 18 3 3 1k 15 3m 5k (eq. 16) in nominal conditions, the plateau establishes to around 14 v. given the divide?by?6 ratio, the opp pin will swing to 14/6 = 2.3 v during normal conditions, leaving 700 mv margin. a 100 pf capacitor can be added between the opp pin and gnd to improve noise immunity and avoid erratic trips in presence of external surges. do not increase this capacitor too much otherwise the opp signal will be af fected by the integrating time constant. a second solution for the ovp detection alone, is to use a zener diode wired as recommended by. d3 15v 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 1k roppu 421k 11 d2 1n4148 c1 22pf ovp figure 49. a zener diode in series with a diode helps to improve the noise immunity of the system for this configuration to maintain an 18 v level, we have selected a 15 v zener diode. in nominal conditions, the voltage on the opp pin is almost 0 v during the off time as the zener is fully blocked. this technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in figure 48. please note the reduction of the capacitor on the opp pin to 10 pf ? 22 pf. this capacitor is necessary because of the potential spike coupling through the zener parasitic capacitance from the bias winding due to the leakage inductance. despite the 1 s blanking delay at turn off. this spike is energetic enough to charge the added capacitor c 1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. when implementing the zener option, it is important to carefully observe the opp pin voltage (short probe connections!) and check that enough margin exists to that respect. over temperature protection in a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases above a certain value. figure 50 shows how to implement a simple otp using an external ntc and a series diode. the principle remains the same: make sure the opp network is not affected by the additional ntc hence the presence of this isolation diode. when the ntc resistance decreases as the temperature increases, the voltage on the opp pin during the off time will slowly increase and, once it passes 3 v for 4 consecutive clock cycles, the controller will permanently latch off.
ncp1251 www. onsemi.com 22 op p vlatch vcc au x. winding opp roppl 2.5k nt c d2 1n4148 roppu 841k full?latch figure 50. the internal circuitry hooked to pin 3 can be used to implement over temperature protection (otp) back to our 19 v adapter, we have found that the plateau voltage on the auxiliary diode was 13 v in nominal conditions. we have selected an ntc which offers a resistance of 470 k at 25 c and drops to 8.8 k at 110 c. if our auxiliary winding plateau is 14 v and we consider a 0.6 v forward drop for the diode, then the voltage across the ntc in fault mode must be: v ntc 14 3 0.6 10.4 v (eq. 17) based on the 8.8 k ntc resistor at 110 c, the current through the device must be: i ntc 10.4 8.8k 1.2 ma (eq. 18) as such, the bottom resistor r oppl , can easily be calculated: r oppl 3 1.2m 2.5 k (eq. 19) now that the pulldown opp resistor is known, we can calculate the upper resistor value r oppu to adjust the power limit at the chosen output power level. suppose we need a 200 mv decrease from the 0.8 v set point and the on?time swing on the auxiliary anode is ?67.5 v, then we need to drop over r oppu a voltage of: v roppu 67.5 0.2 67.3 v (eq. 20) the current flowing in the pulldown resistor r oppl in this condition will be: i roppu 200m 2.5k 80 a (eq. 21) the r oppu value is therefore easily derived: r oppu 67.3 80 841 k (eq. 22) combining ovp and otp the otp and zener?based ovp can be combined together as illustrated by figure 51.
ncp1251 www. onsemi.com 23 4 5 1 opp vlatch 10 8 9 vcc au x. winding opp roppl 2.5k 11 nt c d2 1n4148 roppu 841k d3 15v ovp figure 51. with the ntc back in place, the circuit nicely combines ovp, otp and opp on the same pin in nominal v cc / output conditions, when the zener is not activated, the ntc can drive the opp pin and trigger the adapter in case of an over temperature. during nominal temperature if the loop is broken, the voltage runaway will be detected and the controller will shut down the converter. in case the opp pin is not used for either opp or ovp, it can simply be grounded. filtering the spikes the auxiliary winding is the seat of spikes that can couple to the opp pin via the parasitic capacitances exhibited by the zener diode and the series diode. to prevent an adverse triggering of the over voltage protection circuitry, it is possible to install a small rc filter before the detection network. typical values are those given in figure 52 and must be selected to provide the adequate filtering function without degrading the stand?by power by an excessive current circulation. latched ovp on v cc the v cc pin is permanently monitored by a comparator. when the v cc exceeds 25.5 v (typical), all pulses are immediately stopped and the v cc falls to the scr latched-level around 7 v typical. the controller remains in this state as long as a sufficient current flows in the scr, at least 30 a. we recommend to put a design margin there, with a minimum current around 60 a at the lowest input line. with the c version, the ovp on v cc is autorecovery. 4 5 1 op p vlatch 10 3 9 vcc aux. winding opp roppl 2.5k 11 nt c 2 d2 1n4148 roppu 841k d3 15v ovp r3 220 c1 330pf ad d ition al fil ter figure 52. a small rc filter avoids the fast rising spikes from reaching the protection pin of the ncp1251 in presence of energetic perturbations superimposed on the input line
ncp1251 www. onsemi.com 24 package dimensions case 318g?02 issue v 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1251/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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